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? semiconductor components industries, llc, 2013 august, 2013 ? rev. 0 1 publication order number: nb3v8312c/d nb3v8312c ultra-low jitter, low skew 1:12 lvcmos/lvttl fanout buffer the nb3v8312c is a high performance, low skew lvcmos fanout buffer which can distribute 12 ultra ? low jitter clocks from an lvcmos/lvttl input up to 250 mhz. the 12 lvcmos output pins drive 50 series or parallel terminated transmission lines. the outputs can also be disabled to a high impedance (tri ? stated) via the oe input, or enabled when high. the nb3v8312c provides an enable input, clk_en pin, which synchronously enables or disables the clock outputs while in the low state. since this input is internally synchronized to the input clock, changing only when the input is low, potential output glitching or runt pulse generation is eliminated. separate v dd core and v ddo output supplies allow the output buffers to operate at the same supply as the v dd (v dd = v ddo ) or from a lower supply voltage. compared to single ? supply operation, dual supply operation enables lower power consumption and output ? level compatibility. the v dd core supply voltage can be set to 3.3 v, 2.5 v or 1.8 v, while the v ddo output supply voltage can be set to 3.3 v, 2.5 v, or 1.8 v, with the constraint that v dd v ddo . this buffer is ideally suited for various networking, telecom, server and storage area networking, rru lo reference distribution, medical and test equipment applications. features ? power supply modes: v dd (core) / v ddo (outputs) 3.3 v / 3.3 v 3.3 v / 2.5 v 3.3 v / 1.8 v 2.5 v / 2.5 v 2.5 v / 1.8 v 1.8 v / 1.8 v ? 250 mhz maximum clock frequency ? accepts lvcmos, lvttl clock inputs ? lvcmos compatible control inputs ? 12 lvcmos clock outputs ? synchronous clock enable ? output enable to high z state control ? 150 ps max. skew between outputs ? temp. range ? 40 c to +85 c ? 32 ? pin lqfp and qfn packages ? these are pb ? free devices applications ? networking ? telecom ? storage area network end products ? servers ? routers ? switches lqfp ? 32 fa suffix case 873a see detailed ordering and shipping information on page 9 of this data sheet. ordering and marking information http://onsemi.com figure 1. simplified logic diagram q0 q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q d clk_en clk oe gnd v ddo v dd qfn32 mn suffix case 488am 32 1 r pu r pu r pd
nb3v8312c http://onsemi.com 2 figure 2. lqfp ? 32 pinout configuration (top view) q11 v ddo q10 gnd q9 v ddo q8 gnd q0 v ddo q1 gnd q2 v ddo q3 gnd gnd gnd gnd gnd q7 v ddo q6 gnd q5 q4 v ddo v dd clk_en clk oe v dd figure 3. qfn32 pinout configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 exposed nb3v8312c 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 gnd gnd gnd v dd clk_en clk oe v dd gnd q7 v ddo q6 gnd q5 q4 v ddo 32 31 25 26 30 27 28 29 910 16 15 11 14 13 12 q0 v ddo q1 gnd q2 v ddo q3 gnd q11 v ddo q10 gnd q9 v ddo q8 gnd nb3v8312c pad (ep) table 1. pin description pin name i/o open default description 1, 5, 8, 12, 16, 17, 21, 25, 29 gnd power ground, negative power supply 2, 7 vdd power positive supply for core and inputs 3 clk_en input high synchronous clock enable input. when high, outputs are enabled. when low, outputs are disabled low. internal pullup resistor. 4 clk input low single ? ended clock input; lvcmos/lvttl. internal pull ? down resistor. 6 oe input high output enable. internal pullup resistor. 9, 11, 13, 15, 18, 20, 22, 24, 26, 28, 30, 32 q11, q10, q9, q8, q7, q6, q5, q4, q3, q2, q1, q0 output single ? ended lvcmos/lvttl outputs 10, 14, 19, 23, 27, 31 vddo power positive supply for outputs ? ep ? ? the exposed pad (ep) on the package bottom is ther- mally connected to the die for improved heat transfer out of package. the exposed pad must be attached to a heat ? sinking conduit. the pad is connected to the die and must only be connected electrically to gnd on the pc board. 1. all vdd, vddo and gnd pins must be externally connected to a power supply to guarantee proper operation. bypass each supply p in with 0.01 f to gnd.
nb3v8312c http://onsemi.com 3 figure 4. clk_en control timing diagram clk clk_en q table 2. oe, clk_en function tables inputs outputs oe clk_en (note 2) clk q[0:11] 0 x x hi ? z 1 0 x low 1 1 0 low 1 1 1 high 2. the clk_en control input synchronously enables or disables the outputs as shown in figure 4. this control latches on the falling edge of the selected input clk. when clk_en is low, the outputs are disabled in a low state. when clk_en is high, the outputs are enabled as shown. clk_en to clk set up and hold times must be satisfied.
nb3v8312c http://onsemi.com 4 table 3. attributes (note 3) characteristics value internal input pullup (r pu ) and pulldown (r pd ) resistor 50 k input capacitance, c in 4 pf power dissipation capacitance, c pd (per output) 20 pf r out 8 esd protection human body model machine model > 1.5 kv > 200 v moisture sensitivity, indefinite time out of drypack (note 3) level 1 flammability rating oxygen index ul ? 94 code v ? 0 a 1/8? 28 to 34 transistor count 464 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 3. for additional information, see application note and8003/d. table 4. maximum ratings (note 4) symbol parameter condition rating unit v dd / v ddo positive power supply gnd = 0 v 4.6 v v i input voltage ? 0.5 v i v dd + 0.5 v t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) (note 5) 0 lfpm 500 lfpm lqfp ? 32 lqfp ? 32 80 55 c/w c/w jc thermal resistance (junction ? to ? case) (note 5) standard board lqfp ? 32 lqfp ? 32 12 ? 17 c/w ja thermal resistance (junction ? to ? ambient) (note 5) 0 lfpm 500 lfpm qfn 32 qfn 32 31 27 c/w jc thermal resistance (junction ? to ? case) (note 5) standard board qfn 32 12 c/w stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 4. maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simu ltaneously. if stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected. 5. jedec standard multilayer board ? 2s2p (2 signal, 2 power).
nb3v8312c http://onsemi.com 5 table 5. lvcmos/lvttl dc characteristics (t a = ? 40 c to +85 c) symbol characteristics conditions min typ max unit v ih input high voltage v dd = 3.465 v 2.0 v dd + 0.3 v v dd = 2.625 v 1.7 v dd + 0.3 v v dd = 2.0 v 0.65 x v dd v dd + 0.3 v v il input low voltage v dd = 3.465 v ? 0.3 1.3 v v dd = 2.625 v ? 0.3 0.7 v v dd = 2.0 v ? 0.3 0.35 x v dd v i ih input high current clk v dd = v in = 3.465 v or 2.625 v or 2.0 v 150 a oe, clk_en 5 i il input low current clk v dd = 3.465 v or 2.625 v or 2.0 v, v in = 0 v ? 5 a oe, clk_en ? 150 v oh output high voltage (note 6) v ddo = 3.3 v 5% 2.6 v v ddo = 2.5 v 5% 1.8 v ddo = 2.5 v 5%; i oh = ? 1 ma 2.0 v ddo = 1.8 v 0.2 v v dd ? 0.4 v ddo = 1.8 v 0.2 v; i oh = ? 100 a v dd ? 0.2 v ol output low voltage (note 6) v ddo = 3. 3v 5% 0.5 v v ddo = 2.5 v 5% 0.45 v ddo = 2.5 v 5%; i ol = 1 ma 0.4 v ddo = 1.8 v 0.2 v 0.35 v ddo = 1.8 v 0.2 v; i ol = 100 a 0.2 note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. outputs terminated 50 to v ddo /2 unless otherwise specified. see figure 7. table 6. power supply dc characteristics , (t a = ? 40 c to +85 c) v dd (core) v ddo (outputs) min typ max unit 3.3 v 5% 3.3 v 5% 10 ma 3.3 v 5% 2.5 v 5% 10 ma 3.3 v 5% 1.8 v 0.2v 10 ma 2.5 v 5% 2.5 v 5% 10 ma 2.5 v 5% 1.8 v 0.2v 10 ma 1.8 v 0.2 v 1.8 v 0.2v 10 ma
nb3v8312c http://onsemi.com 6 table 7. ac characteristics (t a = ? 40 c to +85 c) (note 7) symbol characteristic min typ max unit f max maximum operating frequency v dd / v ddo 3.3 v 5% / 3.3 v 5% 3.3 v 5% / 2.5 v 5% 3.3 v 5% / 1.8 v 0.2 v 2.5 v 5% / 2.5 v 5% 2.5 v 5% / 1.8 v 0.2 v 1.8 v 0.2 v / 1.8 v 0.2 v 250 250 200 250 200 200 mhz t plh propagation delay, low to high; (note 8) v dd / v ddo 3.3 v 5% / 3.3 v 5% 3.3 v 5% / 2.5 v 5% 3.3 v 5% / 1.8 v 0.2 v 2.5 v 5% / 2.5 v 5% 2.5 v 5% / 1.8 v 0.2 v 1.8 v 0.2 v / 1.8 v 0.2 v 0.9 1.0 1.0 1.3 1.3 2.4 2.2 2.3 3.0 3.1 3.5 4.2 ns t jit additive phase jitter, rms; v dd / v ddo f c = 100 mhz 3.3 v 5% / 3.3 v 5% integration range: 12 khz ? 20 mhz 3.3 v 5% / 2.5 v 5% see figure 5 3.3 v 5% / 1.8 v 0.2 v 2.5 v 5% / 2.5 v 5% 2.5 v 5% / 1.8 v 0.2 v 1.8 v 0.2 v / 1.8 v 0.2 v 30 40 50 20 100 130 fs t sk(o) output ? to ? output skew; (note 9); figure 6 v dd / v ddo 3.3 v 5% / 3.3 v 5% 3.3 v 5% / 2.5 v 5% 3.3 v 5% / 1.8 v 0.2 v 2.5 v 5% / 2.5 v 5% 2.5 v 5% / 1.8 v 0.2 v 1.8 v 0.2 v / 1.8 v 0.2 v 125 135 145 150 150 140 ps t sk(pp) part ? to ? part skew; (note 10) v dd / v ddo 3.3 v 5% / 3.3 v 5% 3.3 v 5% / 2.5 v 5% 3.3 v 5% / 1.8 v 0.2 v 2.5 v 5% / 2.5 v 5% 2.5 v 5% / 1.8 v 0.2 v 1.8 v 0.2 v / 1.8 v 0.2 v 250 250 250 250 250 250 ps t r /t f output rise and fall times v dd / v ddo 3.3 v 5% / 3.3 v 5% 3.3 v 5% / 2.5 v 5% 3.3 v 5% / 1.8 v 0.2 v 2.5 v 5% / 2.5 v 5% 2.5 v 5% / 1.8 v 0.2 v 1.8 v 0.2 v / 1.8 v 0.2 v 200 200 200 200 200 200 700 700 700 700 700 800 ps odc output duty cycle (note 11) v dd / v ddo f 200 mhz, 3.3 v 5% / 3.3 v 5% f 150 mhz, 3.3 v 5% / 2.5 v 5% f 100 mhz, 3.3 v 5% / 1.8 v 0.2 v f 150 mhz, 2.5 v 5% / 2.5 v 5% f 100 mhz, 2.5 v 5% / 1.8 v 0.2 v f 100 mhz, 1.8 v 0.2 v / 1.8 v 0.2 v 45 45 45 45 45 45 55 55 55 55 55 55 % all parameters measured at f max unless noted otherwise. 7. outputs loaded with 50 to v ddo /2; see figure 7. clock input with 50% duty cycle; minimum input amplitude = 1.2 v at v dd = 3.3 v, 1.0 v at v dd = 2.5 v, v dd /2 at v dd = 1.8 v. 8. measured from the v dd /2 of the input to v ddo /2 of the output. 9. defined as skew between outputs at the same supply voltage and with equal load conditions. measured at v ddo /2. 10. defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. using the same type of input on each device, the output is measured at v ddo /2. 11. clock input with 50% duty cycles, rail ? to ? rail amplitude and t r /t f = 500 ps.
nb3v8312c http://onsemi.com 7 figure 5. typical phase noise plot at f carrier = 100 mhz at an operating voltage of 3.3 v, room temperature nb3v8312c additive phase jitter @ 100 mhz vdd = vddo = 3.3 v 12 khz to 20 mhz = 29.8 fs (typical) filter = 12 khz ? 20 mhz source rms jitter = 200.53 fs output rms jitter = 202.73 fs rms addititive jitter rms phase jitter of output 2 rms phase jitter of input 2 29.8 202.73 fs 2 200.53 fs 2 output (dut + source) input source the above phase noise data was captured using agilent e5052a/b. the data displays the input phase noise and output phase noise used to calculate the additive phase jitter at a specified integration range. the rms phase jitter contributed by the device (integrated between 12 khz and 20 mhz) is 29.8 fs. the additive phase jitter performance of the fanout buffer is highly dependent on the phase noise of the input source. to obtain the most accurate additive phase noise measurement, it is vital that the source phase noise be notably lower than that of the dut. if the phase noise of the source is greater than the device under test output, the source noise will dominate the additive phase jitter calculation and lead to an artificially low result for the additive phase noise measurement within the integration range. the figure above is a good example of the nb3v8312c source generator phase noise having a significantly higher floor such that the dut output results in an additive phase jitter of 29.8 fs. rms addititive jitter rms phase jitter of output 2 rms phase jitter of input 2 29.8 202.73 fs 2 200.53 fs 2
nb3v8312c http://onsemi.com 8 figure 6. ac reference measurement v ihcmr gnd t phl t lh clk clk qx qx t pw t p v dd 2 t skewdc % t pw t p 100 v dd 2 v dd 2 v dd 2 v ddo 2 v ddo 2 v ddo 2 v ddo 2 v ddo 2 lvcmos_clk v pp = v ih ? v il in z o = 50 nb3v8312c scope 50 v dd v ddo gnd figure 7. typical device evaluation and termination setup ? see table 8 v ddo 2 = 0 v = ground q x table 8. test supply setup. v ddo supply may be centered on 0.0 v (scope gnd) to permit direct connection into ?50 to gnd? scope module. v dd supply tracks dut gnd pin spec condition: v dd test setup vddo test setup gnd pin test setup v dd = 3.3 v 5%, v ddo = 3.3 v 5% +1.65 5% +1.65 v 5% ? 1.65 v 5% v dd = 3.3 v 5%, v ddo = 2.5 v 5% +2.05 v 5% +1.25 v 5% ? 1.25 v 5% v dd = 3.3 v 5%, v ddo = 1.8 v 5% +2.4 v 5% +0.9 v 0.1 v ? 0.9 v 0.1 v v dd = 2.5 v 5%, v ddo o = 2.5 v 5% +1.25 v 5% +1.25 v 5% ? 1.25 v 5% v dd = 2.5 v 5%, v ddo = 1.8 v 0.2 v +1.6 v 5% +0.9 v 0.1 v ? 0.9 v 0.1 v v dd = 1.8 v 0.2 v, v ddo = 1.8 v 0.2 v +0.9 v 0.1 v +0.9 v 0.1 v ? 0.9 v 0.1 v
nb3v8312c http://onsemi.com 9 marking diagrams* *for additional marking information, refer to application note and8002/d. (*note: microdot may be in either location) a = assembly location wl = wafer lot yy = year ww = work week g = pb ? free package nb3v 8312c awlyywwg nb3v 8312c awlyywwg 1 32 lqfp ? 32 qfn32 ordering information device package shipping ? nb3v8312cfag lqfp ? 32 (pb ? free) 250 units / tray nb3v8312cfar2g lqfp ? 32 (pb ? free) 2000 / tape & reel NB3V8312CMNG qfn32 (pb ? free) 74 units / rail nb3v8312cmnr4g qfn32 (pb ? free) 1000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nb3v8312c http://onsemi.com 10 package dimensions 32 lead lqfp case 873a ? 02 issue c detail y a s1 v b 1 8 9 17 25 32 ae ae p detail y base n j d f metal section ae ? ae g seating plane r q w k x 0.250 (0.010) gauge plane e c h detail ad detail ad a1 b1 v1 4x s 4x 9 ? t ? ? z ? ? u ? t-u 0.20 (0.008) z ac t-u 0.20 (0.008) z ab 0.10 (0.004) ac ? ac ? ? ab ? m 8x ? t ? , ? u ? , ? z ? t-u m 0.20 (0.008) z ac notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ? ab ? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ? t ? , ? u ? , and ? z ? to be determined at datum plane ? ab ? . 5. dimensions s and v to be determined at seating plane ? ac ? . 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ? ab ? . 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.520 (0.020). 8. minimum solder plate thickness shall be 0.0076 (0.0003). 9. exact shape of each corner may vary from depiction. dim a min max min max inches 7.000 bsc 0.276 bsc millimeters b 7.000 bsc 0.276 bsc c 1.400 1.600 0.055 0.063 d 0.300 0.450 0.012 0.018 e 1.350 1.450 0.053 0.057 f 0.300 0.400 0.012 0.016 g 0.800 bsc 0.031 bsc h 0.050 0.150 0.002 0.006 j 0.090 0.200 0.004 0.008 k 0.450 0.750 0.018 0.030 m 12 ref 12 ref n 0.090 0.160 0.004 0.006 p 0.400 bsc 0.016 bsc q 1 5 1 5 r 0.150 0.250 0.006 0.010 v 9.000 bsc 0.354 bsc v1 4.500 bsc 0.177 bsc b1 3.500 bsc 0.138 bsc a1 3.500 bsc 0.138 bsc s 9.000 bsc 0.354 bsc s1 4.500 bsc 0.177 bsc w 0.200 ref 0.008 ref x 1.000 ref 0.039 ref
nb3v8312c http://onsemi.com 11 package dimensions qfn32 5x5, 0.5p case 488am issue o seating 32 x k 0.15 c (a3) a a1 d2 b 1 9 16 17 32 2 x 2 x e2 32 x 8 24 32 x l 32 x bottom view exposed pad top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c 25 e a 0.10 b c 0.05 c notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm terminal 4. coplanarity applies to the exposed pad as well as the terminals. plane dim min nom max millimeters a 0.800 0.900 1.000 a1 0.000 0.025 0.050 a3 0.200 ref b 0.180 0.250 0.300 d 5.00 bsc d2 2.950 3.100 3.250 e 5.00 bsc e2 e 0.500 bsc k 0.200 ??? ??? l 0.300 0.400 0.500 2.950 3.100 3.250 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 pitch 3.20 0.28 3.20 32 x 28 x 0.63 32 x 5.30 5.30 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 nb3v8312c/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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